#
#	PROJECT NAME
#
PROJECT = handpie

#
# paths of each directories
#
SRC_DIR = src
OBJ_DIR = obj

#
# directories list that indicates where header files be located.
#
INCLUDE_DIRS += includes
INCLUDE_DIRS +=
#
# directories list that indicates where libary files be located.
#
LIB_DIRS +=
#
# libraries list that project use
#
LIBS += pthread
LIBS +=

#
# compiler options
#
INCLUDES = $(addprefix -I, $(INCLUDE_DIRS))
CFLAGS += $(INCLUDES)
CFLAGS += $(shell pkg-config --cflags opencv)
CFLAGS +=
#
# linker options
#
LDFLAGS += $(addprefix -L, $(LIB_DIRS))
LDFLAGS +=
LDLIBS += $(addprefix -l, $(LIBS))
LDLIBS += $(shell pkg-config --libs opencv)
LDLIBS +=

#
# debug or release (e.g. $ make DEBUG=1)
# 
ifeq ($(DEBUG), 1) # for debugging
CFLAGS += -DDEBUG -O0 -g -Wall -W
BUILD = $(addsuffix _debug, $(PROJECT))
else ifeq ($(RELEASE), 1) # for release
CFLAGS += -O2
BUILD = $(addsuffix _release, $(PROJECT))
else # for ordinary time
CFLAGS += -DDEBUG -O1 -Wall -W -Wno-unused-variable -Wno-unused-parameter
BUILD = $(addsuffix _dev, $(PROJECT))
endif

#
# <경> 손  대  지  마  시  오  <고>
# DO NOT EDIT BELOW
#
#

# commands
CC = g++
LD = g++
RM = rm -rfv
MKDIR = mkdir

# dependency file name 
DEP_FILE = $(PROJECT).d

# source files list to be compiled to object files
TARGET_SRCS = $(notdir $(wildcard $(SRC_DIR)/*.cpp))
# object files list needed for project
TARGET_OBJS = $(TARGET_SRCS:%.cpp=$(OBJ_DIR)/%.o)
	
# header files
HEADERS = $(wildcard $(INCLUDE_DIRS)/*.h)

# suffixes rules
.SUFFIXES: .cpp .o

# fake targets (don't create file as a result of make)
.PHONY: all clean

# build project entirely
all: $(DEP_FILE) $(BUILD)

# link all object files to make executable binary file
LD_CMD = $(strip $(LD) $(LDFLAGS) $(LDLIBS) -o $(BUILD) $^)
$(BUILD): $(TARGET_OBJS)
	@echo "$(MAKE): link: $(LD_CMD)"
	@$(LD_CMD)

# compile .cpp to .o files
CC_CMD = $(strip $(CC) $(CFLAGS) -c $< -o $@)
$(OBJ_DIR)/%.o: $(SRC_DIR)/%.cpp
	@[ -d $(OBJ_DIR) ] || $(MKDIR) -p $(OBJ_DIR)
	@echo "$(MAKE): compile $<: $(CC_CMD)"
	@$(CC_CMD)

# analyze dependency of each files
.SECONDEXPANSION:
$(DEP_FILE): $(HEADERS)
	@[ -d $(OBJ_DIR) ] || $(MKDIR) $(OBJ_DIR)
	@rm -f $(DEP_FILE)
	@echo "$(MAKE): analyze dependency of each files..."
	@for FILE in $(TARGET_SRCS:%.cpp=%); do \
		$(CC) $(INCLUDES) -MM -MT $(OBJ_DIR)/$$FILE.o $(SRC_DIR)/$$FILE.cpp >> $(DEP_FILE); \
	done

# remove all generated by makefile
clean:
	@$(RM) $(BUILD)
	@$(RM) $(DEP_FILE)
	@$(RM) $(OBJ_DIR)

#
# dependent relationship.
# If something that a target is dependent on was changed at least 1 of lists, the target will be re-compiled.
#
ifneq ($(MAKECMDGOALS), clean)
ifneq ($(MAKECMDGOALS), depend)
ifneq ($(strip $(TARGET_SRCS)),)
-include $(DEP_FILE)
endif
endif
endif
